U.S. Pat. No. 6,671,204, titled “non-volatile memory device with page buffer having dual registers and methods of using the same”, describes a page buffer design with cache program and copy-back functions. FIG. 1 illustrates the schematic diagram of Page Register and Sense Amplifier (S/A) block 120. The Page Register and S/A block 120 is coupled between a memory cell array 110 and a Y-gating circuit 130. The Page Register and Sense Amplifier (S/A) block 120 includes a bit line control circuit 140 and a page buffer 122. The page buffer 122 has a sense line 125 that connected to the bit line control circuit 140 through a sense node E.
The bit line control circuit 140 includes four NMOS transistors 141, 142, 143 and 144. The NMOS transistors 141 and 142 are serially coupled between bit lines BLE and BLO, and are controlled by control signals VBLE and VBLO, respectively. The drains of transistors 141 and 142 are commonly coupled to a signal line VIRPWR. The NMOS transistor 143 is coupled between the bit line BLE and the sense node E, and is controlled by a control signal BLSHFE. The NMOS transistor 144 is coupled between the bit line BLO and the sense node E, and is controlled by a control signal BLSHFO.
The page buffer 122 has a main register 150 and an auxiliary register 170; both are connected to the sense line 125. The main register 150 includes two NMOS transistors 151 and 152, two inverters 153 and 154, and a PMOS transistor 155. The data is stored in a main latch 156, formed by inverters 153 and 154. The PMOS transistor 155 serves as a pre-charge circuit for the main latch 156. The auxiliary register 170 includes two NMOS transistors 171 and 172, two inverters 173 and 174, and a PMOS transistor 175. The inverters 173 and 174 form an auxiliary latch 176. The PMOS transistor 175 serves as a pre-charge circuit for the auxiliary latch 176. An NMOS transistor 181 controlled by a control signal PDUMP serves as a switch for data transmission between the auxiliary register 170 and the main register 150 through the sense line 125. NMOS transistors 182 and 183 are provided for controlling data storage from a data line 131 to the auxiliary register 170, and are performed responsive to external control signals DI and nDI, respectively. A PMOS transistor 148 provides current to the bit lines BLE and BLO through the sense line 125 during reading. The PMOS transistor 148 is connected between a power voltage and the sense line 125, and is controlled by a control signal PLOAD.
An NMOS transistor 184 is turned on to connect the main register 150 and a selected bit line BLE or BLO when data to be programmed is transferred to the selected bit line BLE or BLO from the main register 150. An NMOS transistor 185, controlled by a control signal PBDO, outputs read-out data from the selected bit line to the exterior of the page buffer 122. A transistor 186 is provided for checking the program state, and provides program pass or fail information at a node B of the main register 150.
The Y-gating circuit 130 is between the page buffer circuit 120 and the data line 131. The Y-gating circuit 130 is constituted of two NMOS transistors 132 and 133 that are controlled by signals YA and YB, respectively.
During a cache program operation, the external input data is stored in the auxiliary register 170 first, and then is transmitted to the main register 150 through the sense line 125 for programming and verification. During a copy-back function, the data in a memory cell array 110 is read out and stored to the auxiliary register 170 first. After new data is inputted to the auxiliary register 170, the whole page data is transferred to the main register 150 for programming and verification. Because the data have to be transferred between the main register 150 and the auxiliary register 170, its programming procedure is relatively complicated. Moreover, it spends more time during the data transfer process.